Complementary metal oxide semiconductor (CMOS) devices, such as metal oxide semiconductor field-effect transistors (MOSFETs), are commonly used in the fabrication of ultra-large scale integrated (ULSI) devices. The continuing trend is to reduce the size of the devices and to lower the power consumption requirements. Size reduction of the MOSFETs has enabled the continued improvement in speed, performance, density, and cost per unit function of integrated circuits. Significant challenges, however, are faced as the size of CMOS devices continue to decrease.
For example, as the length of the gate electrode of a MOSFET is reduced, the source and drain regions increasingly interact with the channel and gain influence on the channel potential and the gate dielectric. Consequently, a transistor with a short gate length suffers from problems related to the inability of the gate electrode to substantially control the on and off states of the channel. Phenomena such as reduced gate control associated with transistors with short channel lengths are termed short-channel effects.
One method of reducing the influence of the source and drain on the channel and the gate dielectric is to use graded junctions. Graded junctions are formed by performing multiple ion implants in the source and drain regions. Generally, the area of the source and drain regions adjacent to the gate electrode is lightly doped, and the area of the source and drain regions farther away from the gate electrodes is doped heavier.
Shallow lightly-doped areas have been fabricated by lowering the implant energy and increasing the dose or ion concentration. Because the implant energy is lowered, the depth of the implant region is small, and because the dose or ion concentration is increased, the areas are less resistive. As a result, a shallow area having low electrical resistance is created. This method, however, may exhibit degraded activation and anomalous enhancement in the diffusion.
Accordingly, what is needed in the art is improved source/drain regions.